The present invention relates to security fuses for programmable logic array devices.
Programmable logic devices typically use fuses or memory cells which serve to provide desired connections to form a logic network. The fuses or memory cells are blown or written into (programmed) in accordance with the desired logic function. To verify that the circuit has been correctly configured, this fuse or memory array can then be read to check the programming.
In order to prevent competitors from reading out the programming of the logic chip, a security fuse is often used. The security fuse, when programmed, disables the reading of the memory or fuse array.
A typical prior art configuration is shown in FIG. 1. A memory array 10 is programmed with data inputs so that it will perform logic functions between logic inputs and logic outputs. The program data out from memory array 10 is ANDed in a series of AND gates 12 with a signal from a security fuse 14. When security fuse 14 is blown, or written to, a zero logic level will be presented to one input of each of AND gates 12. This disables the gate outputs and provides for an all zero data output reading regardless of the actual configuration of memory array 10, thus preventing a competitor from getting the program.
The arrangement of FIG. 1 requires that the programmer verify the programming prior to setting the security fuse. Once the security fuse is set, the programmed information can no longer be verified. In the event that the setting of the security fuse causes an error elsewhere in the circuit, this will not be detectable during a program verification. Typically, security fuse 14 is located in memory array 10 near other data fuses and it could cause errors in other data elements when it is set if there is a defect.